944 Chapter 25
Figure 25-113. Rider pot multiplexing and address decoding.
Figure 25-114. An A/D converter (as part of the system in Fig. 25-113).
Multiplexted
bus to A/D
converter
Sixteen
rider pots
1/4 4011
1/4 4011
0 1 2 3 4
Channel
select
line
1/4 4011
4028
1/4 4011
3
2
1
0
Select
outputs
to switch
(5, 2, B, A)
VAD (Valid A/D decode address)
4028
Address bus
4051
4051
Multiplex
analogue
bus
Multiturn
zero trim
10 V reference
Bus buffer
AD507Gain trim
AD7574
Up
1/4 4011
RD
Busy
10 V reference Wait R/W 0 1 2 3 4 5 6 7 VAD Data Bus
Valid A/D decide address
+5 V