Reverse Engineering for Beginners

CHAPTER 22. UNIONS CHAPTER 22. UNIONS

lw $t9, (time & 0xFFFF)($gp)

or $at, $zero ; load delay slot, NOP

jalr $t9

move $a0, $zero ; branch delay slot

lui $s2, ($LC1 >> 16) # "%f\n"

move $a0, $v0

la $s2, ($LC1 & 0xFFFF) # "%f\n"

move $s0, $zero

jal my_srand

li $s1, 0x64 # 'd' ; branch delay slot

loc_104:
jal float_rand
addiu $s0, 1
lw $gp, 0x28+var_18($sp)
; convert value we got from float_rand() to double type (printf() need it):
cvt.d.s $f2, $f0
lw $t9, (printf & 0xFFFF)($gp)
mfc1 $a3, $f2
mfc1 $a2, $f3
jalr $t9
move $a0, $s2
bne $s0, $s1, loc_104
move $v0, $zero
lw $ra, 0x28+var_4($sp)
lw $s2, 0x28+var_8($sp)
lw $s1, 0x28+var_C($sp)
lw $s0, 0x28+var_10($sp)
jr $ra
addiu $sp, 0x28 ; branch delay slot

$LC1: .ascii "%f\n"<0>
$LC0: .float 1.0

There is also an useless LUI instruction added for some weird reason. We considered this artifact earlier:17.5.6 on page 216.

22.1.3 ARM (ARM mode).

Listing 22.3: Optimizing GCC 4.6.3 (IDA)

float_rand
STMFD SP!, {R3,LR}
BL my_rand
; R0=pseudorandom value
FLDS S0, =1.0
; S0=1.0
BIC R3, R0, #0xFF000000
BIC R3, R3, #0x800000
ORR R3, R3, #0x3F800000
; R3=pseudorandom value & 0x007fffff | 0x3f800000
; copy from R3 to FPU (register S15).
; it behaves like bitwise copy, no conversion done:
FMSR S15, R3
; subtract 1.0 and leave result in S0:
FSUBS S0, S15, S0
LDMFD SP!, {R3,PC}

flt_5C DCFS 1.0

main
STMFD SP!, {R4,LR}
MOV R0, #0
BL time
BL my_srand
MOV R4, #0x64 ; 'd'

loc_78
BL float_rand
; S0=pseudorandom value