Audio Engineering

Preamplifi ers and Input Signals 195

It is often found that the chip construction employed for junction FETs is symmetrical, so
that the source and drain are interchangeable in use. For such devices the circuit symbol
shown in Figure 7.27(c) should be used properly.

A practical problem with lateral devices, in which the current fl ow through the device
is parallel to the surface of the chip, is that the path length from source to drain, and
hence the device impedance and current carrying capacity, is limited by the practical
problems of defi ning and etching separate regions that are in close proximity during the
manufacture of the device.

7.10.2.2 V-MOS and T-MOS

This problem is not of very great importance for small signal devices, but is a major
concern in high current ones such as those employed in power output stages. It has led
to the development of MOSFETs in which the current fl ow is substantially in a direction
that is vertical to the surface and in which the separation between layers is determined by
diffusion processes rather than by photolithographic means.

Drain

Gate oxide layer

Substrate and mount

(Source connected to substrate)

Source

Gate

NN

P

G

D

S

Sub

N–ch MOSFET

Figure 7.26 : Chip cross section and circuit symbol for lateral MOSFET (small signal type).

Figure 7.27 : Chip cross section and circuit symbols for (bipolar) junction FET.

Source

Gate

Drain

NNP

P

(Gate connected to substrate)

(a) (b)

G

S

D

(c)

Symmetrical types

G

S/D

D/S