Audio Engineering

516 Chapter 16

If the FIR clock frequency is increased to 176.4 kHz, the action of the shift registers will
be to generate three further signal samples and to interpolate these additional samples
between those given by the original 44.1-kHz sampling intervals—a process termed “ four
times oversampling. ”

The simple sample-and-hold stage, at the output of the DAC shown in Figure 16.10 ,
will also assist fi ltering, as it will attenuate any signals occurring at the clock frequency
to an extent determined by the duration of the sampling operation—called the sampling
“ window. ” If the window length is near 100% of the cycle time, attenuation of the S/H
circuit will be nearly total atfs.

Oversampling, on its own, would have the advantage of pushing the aliasing frequency
up to a higher value, which makes the design of the antialiasing and waveform
reconstruction fi lter a much easier task to accomplish using simple analogue-mode
low-pass fi lters whose characteristics can be tailored so that they introduce very little
unwanted group delay and phase shift. A typical example of this approach is the linear
phase analogue fi lter design, shown in Figure 16.14 , used following the fi nal 16-bit DACs
in the replay chain.

However, the FIR fi lter shown in Figure 16.12 has the additional effect of computing
intermediate numerical values for the samples interpolated between the original
44.1-kHz input data, which makes the discontinuities in the PCM step waveform



 





AF output

C 6

100 pF

R 6

10 K

C 4

1n2

C 3

2n2

22 μF

2K2 2K2

3n9

27n

560 R

1K0

47 R

R 7

R 4 R 5

R 1

R 3

R 2

C 5

C 1

C 2

0V 0V

NE5532

NE5532

U 2

U 1

Analogue

input from DAC

Figure 16.14 : A linear phase LP fi lter.