Video Synchronization 829The binary values P0, P1, P2, and P3 depend on the states of F, V, and H in accordance
with the following table and are used for error detection/correction of timing data:
F V H P3P2F1P0
0 0 0 0 0 0 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 0
1 0 0 0 1 1 1
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 0 0 0 128.8.1.3 Clock Signal
The clock signal is at 27 MHz, there being 1728 clock intervals during each horizontal
line period (PAL).
28.8.1.4 Filter Templates
The remainder of CCIR Recommendation 601 is concerned with the defi nition of the
frequency response plots for presampling and reconstruction fi lter. The fi lters required by
Recommendation 601 are practically diffi cult to achieve and equipment required to meet this
specifi cation has to contain expensive fi lters in order to obtain the required performance.
28.8.2 Parallel Digital Interface
The fi rst digital video interface standards were parallel in format. They consisted of 8
or 10 bits of differential data at ECL data levels and a differential clock signal again
as an ECL signal. Carried via a multicore cable, the signals terminated at either end in
a standard D25 plug and socket. In many ways this was an excellent arrangement and
is well suited to connecting two local digital videotape machines together over a short
distance. The protocol for the digital video interface is shown in Table 28.3. Clock
transitions are specifi ed to take place in the center of each data-bit cell.
Problems arose with the parallel digital video interface over medium/long distances,
resulting in misclocking of input data and visual “ sparkles ” or “ zits ” on the picture.