Chapter3:MemoryManagement
❑ The meaning of thetranslation lookaside bufferis abstracted to refer to a mechanism that translates
a virtual address into a physical address.^38
❑ The kernel regards acacheas a mechanism that provides rapid access to data by reference to a
virtualaddress without the need for a request to RAM memory. There is not always an explicit
difference between data and instruction caches. The architecture-specific code is responsible for
any differentiation if its caches are split in this manner.It is not necessary for each processor type to implement every control function defined by the kernel. If a
function is not required, its invocation can be replaced with an empty operation (do {} while (0))thatis
optimized away by the compiler. This is very frequently the case with cache-related operations because,
as above, the kernel assumes that addressing is based on virtual addresses. The resultant problems do
not occur in physically organized caches so that it is not usually necessary to implement the cache control
functions.The following functions must be made available (even if only as an empty operation) by each CPU-
specific part of the kernel in order to control the TLBs and caches^39 :❑ flush_tlb_allandflush_cache_allflush theentireTLB/cache. This is only required when the
page tables of the kernel (and not of a userspace process) are manipulated because a modification
of this kind affects not only all processes but also all processors in the system.
❑ flush_tlb_mm(struct mm_struct *mm)andflush_cache_mmflush all TLB/cache entries belong-
ing to the address spacemm.
❑ flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
andflush_cache_range(vma, start, end)flush all entries from the TLB/cache between the
startandendvirtual addresses in the address rangevma->vm_mm.
❑ flush_tlb_page(struct vm_area_struct *vma, unsigned long page)and
flush_cache_page(vma, page)flush all entries from the TLB/cache whose virtual addresses are
in an interval that begins atpageand consists ofPAGE_SIZEbytes.
❑ update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)is
invoked after a page fault has been handled. It inserts information in the memory management
unit of the processor so that the entry at the virtual addressaddressis described by the page
table entrypte.
This function is needed only if there is an external MMU. Typically, the MMU is integrated into
the processor, but MIPS processors, for example, have external MMUs.The kernel makes no distinction between data and instruction caches. If a distinction is required, the
processor-specific code can reference theVM_EXECflag invm_area_struct->flagsto ascertain whether
the cache contains data or instructions.Theflush_cache_andflush_tlb_functions very often occur in pairs; for instance, when the address
space of a process is duplicated usingfork.kernel/fork.c
flush_cache_mm(oldmm);
...(^38) Whether TLBs are the only hardware resource for doing this or whether other alternatives (e.g., page tables) are provided is irrele-
vant.
(^39) The following description is based on the documentation by David Miller [Mil] in the kernel sources.