Linux Kernel Architecture

Chapter 14: Kernel Activities

The early versions of kernel 2.6 contained much platform-specific code to handle IRQs that was identical

in many points. Thus, a new, generic IRQ subsystem was introduced during further development of

kernel 2.6. It is able to handle different interrupt controllers and different types of interrupts in a unified

way. Basically, it consists of three abstraction layers as visualized in Figure 14-3:

1. High-Level Interrupt Service Routines (ISRs)— Perform all necessary work caused by the
   interrupt on the device driver’s (or some other kernel component’s) side. If, for instance, a
   device uses an interrupt to signal that some data have arrived, then the job of the high-level
   ISR could be to copy the data to an appropriate place.


2. Interrupt Flow Handling— Takes care of handling the various differences between differ-
   ent interrupt flow types like edge- and level triggering.
   Edge-triggeringmeans that hardware detects an interrupt by sensing a difference in potential
   on the line. Inlevel-triggeredsystems, interrupts are detected when the potential has a specific
   value — the change in potential is not relevant.
   From the kernel viewpoint, level-triggering is more complicated because, after each inter-
   rupt, the line must be explicitly set to the potential that indicates ‘‘no interrupt.’’


3. Chip-Level Hardware Encapsulation— Needs to communicate directly with the underly-
   ing hardware that is responsible to generate interrupts at the electronic level. This layer can
   be seen as some sort of ‘‘device driver‘‘ for interrupt controllers.

Chip specific

Communication Functions

High-level

service routine

handlingFlow Central IRQdatabase Hardware

Figure 14-3: Various types of interrupt handlers and how they are

connected.

Let’s return to the technical side of the problem. The structure used to represent an IRQ descriptor is

(slightly simplified) defined as follows^6 :

<irq.h>

struct irq_desc {

irq_flow_handler_t handle_irq;

struct irq_chip *chip;

(^6) Among some technical elements, support for message signaled interrupts (MSIs) has also been omitted. MSIs are an optional exten-
sion to the PCI standard and a required component of PCI express. They allow for sending an interrupt without using a physical pin
on some piece of hardware, but via a ‘‘message’’ on the PCI bus. Because the number of available pins on modern processors is not
unlimited, but pins are required for many purposes, they are a scarce resource. Hardware designers are thus looking for alternative
methods to send interrupts, and the MSI mechanism is one of them. It will gain increased importance in the future.
Documentation/MSI-HOWTO.txtin the kernel source tree contains some more information about this mechanism.