Chapter 14: Kernel Activities
One particular example for an interrupt controller chip implementation is the IO-APIC on AMD64 sys-
tems. It is given by the following definition:arch/x86/kernel/io_apic_64.c
static struct irq_chip ioapic_chip __read_mostly = {
.name = "IO-APIC",
.startup = startup_ioapic_irq,
.mask = mask_IO_APIC_irq,
.unmask = unmask_IO_APIC_irq,
.ack = ack_apic_edge,
.eoi = ack_apic_level,
#ifdef CONFIG_SMP
.set_affinity = set_ioapic_affinity_irq,
#endif
};Note that the kernel defines the aliashw_interrupt_typeforirq_chip; this is for compatibility with
previous versions of the IRQ subsystem. The name is, for instance, still in use on Alpha systems that
define the chip level operations for the i8259A standard interrupt controller as follows^8 :arch/alpha/kernel/i8529.c
struct hw_interrupt_type i8259a_irq_type = {
.typename = "XT-PIC",
.startup = i8259a_startup_irq,
.shutdown = i8259a_disable_irq,
.enable = i8259a_enable_irq,
.disable = i8259a_disable_irq,
.ack = i8259a_mask_and_ack_irq,
.end = i8259a_end_irq,
};As the code shows, only a subset of all possible handler functions are neecsssary to operate the device.i8259A chips are also still present in many IA-32 systems. Support for this chipset has, however, already
been converted to the more modernirq_chiprepresentation. The interrupt controller type used (and the
allocation of all system IRQs) can be seen in/proc/interrupts. The following example is from a (rather
unchallenged) quad-core AMD64 box:wolfgang@meitner>cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
0: 48 1 0 0 IO-APIC-edge timer
1: 1 0 1 0 IO-APIC-edge i8042
4: 3 0 0 3 IO-APIC-edge
8: 0 0 0 1 IO-APIC-edge rtc
9: 0 0 0 0 IO-APIC-fasteoi acpi
16: 48 48 96720 50082 IO-APIC-fasteoi libata, uhci_hcd:usb1
18: 1 0 2 0 IO-APIC-fasteoi uhci_hcd:usb3, uhci_hcd:usb6,
ehci_hcd:usb7
19: 0 0 0 0 IO-APIC-fasteoi uhci_hcd:usb5
21: 0 0 0 0 IO-APIC-fasteoi uhci_hcd:usb2
22: 407287 370858 1164 1166 IO-APIC-fasteoi libata, libata, HDA Intel
(^8) Usingtypenameinstead ofnameis also obsolete by now, but still supported for compatibility reasons.