VHDL Programming

Data Types 83

END instr;

USE WORK.instr.ALL;

ENTITY mp IS

PORT (instr : IN instruction;

PORT (addr : IN INTEGER;

PORT (data : INOUT INTEGER);

END mp;

ARCHITECTURE mp OF mp IS

BEGIN

PROCESS(instr)

TYPE regtype IS ARRAY(0 TO 255) OF INTEGER;

VARIABLE a, b : INTEGER;

VARIABLE reg : regtype;

BEGIN

--select instruction to

CASE instr is --execute

WHEN lda =>

a := data; --load a accumulator

WHEN ldb =>

b := data; --load b accumulator

WHEN add =>

a := a 1 b; --add accumulators

WHEN sub =>

a := a -b; --subtract accumulators

WHEN sta =>

reg(addr) := a; --put a accum in reg array

WHEN stb =>

reg(addr) := b; --put b accum in reg array

WHEN outa =>

data <= a; --output a accum

WHEN xfr => --transfer b to a

a := b;

END CASE;

END PROCESS;

END mp;

The model receives an instruction stream (instr), an address stream

(addr), and a data stream (data). Based on the value of the enumerated

value of instr, the appropriate instruction is executed. A CASEstatement

is used to select the instruction to execute. The statement is executed and

the process then waits for the next instruction.

Another common example using enumerated types is a state machine.

State machines are commonly used in designing the control logic for ASIC