VHDL Programming

(C. Jardin) #1

88 Chapter Four


USE WORK.array_example.ALL;
ENTITY extract IS
PORT (data : IN data_bus;
PORT (start : IN INTEGER;
PORT (data_out : OUT small_bus);
END extract;

ARCHITECTURE test OF extract IS
BEGIN
PROCESS(data, start)
BEGIN
FOR i IN 0 TO 7 LOOP
data_out(i) <= data(i  start);
END LOOP;
END PROCESS;
END test;

This entity takes in a 32-bit array element as a port and returns 8 bits
of the element. The 8 bits of the element returned depend on the value of
index start. The 8 bits are returned through output port data_out.
(There is a much easier method to accomplish this task, with functions,
described in Chapter 5,“Subprograms and Packages.”)
A change in value of startor datatriggers the process to execute. The
FOR looploops 8 times, each time copying a single bit from port datato
port data_out. The starting point of the copy takes place at the integer
value of port start. Each time through the loop, the ith element of
data_outis assigned the (istart) element of data.
The examples shown so far have been simple arrays with scalar base
types. In the next example, the base type of the array is another array:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
PACKAGE memory IS
CONSTANT width : INTEGER := 3;
CONSTANT memsize : INTEGER := 7;

TYPE data_out IS ARRAY(0 TO width) OF std_logic;
TYPE mem_data IS ARRAY(0 TO memsize) OF data_out;
END memory;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.memory.ALL;
ENTITY rom IS
PORT( addr : IN INTEGER;
PORT( data : OUT data_out;
PORT( cs : IN std_logic);
END rom;
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