VHDL Programming

90 Chapter Four

Addr Bit 3 Bit 2 Bit 1 Bit 0

0 1 2 3 4 5 6 7

0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Figure 4-2
Rom Data Represen-
tation.

The structure of the aggregate must match the structure of the data

type for the assignment to occur. Following is a simple example of an

aggregate assignment:

PROCESS(X)

TYPE bitvec IS ARRAY(0 TO 3) OF BIT;

VARIABLE Y : bitvec;

BEGIN

Y := (‘ 1 ’, ‘ 0 ’, ‘ 1 ’, ‘ 0 ’);

.

.

.

END PROCESS;

Variable Yhas an element of type BITin the aggregate for each element

of its type. In this example, the variable Yis 4 bits wide, and the aggre-

gate is 4 bits wide as well.

The constant rom_datafrom the romexample is an array of arrays.

Each element of type mem_datais an array of type data_out. The aggre-

gate assignment for an array of arrays can be represented by the form

shown here:

value := ((e1, e2,... ,en),... ,(e1, e2,... ,en));

E1... En

This is acceptable, but a much more readable form is shown here: