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VHDL Programming

(C. Jardin) #1

  • Chapter 1 Introduction to VHDL Acknowledgments xviii

    • VHDL Terms

    • Describing Hardware in VHDL

    • Entity

      • Architectures

      • Concurrent Signal Assignment

      • Event Scheduling

      • Statement Concurrency

      • Structural Designs

      • Sequential Behavior

      • Process Statements

      • Process Declarative Region

      • Process Statement Part

      • Process Execution

      • Sequential Statements

      • Architecture Selection

      • Configuration Statements

      • Power of Configurations





  • Chapter 2 Behavioral Modeling

    • Introduction to Behavioral Modeling

    • Transport Versus Inertial Delay

      • Inertial Delay

      • Transport Delay

      • Inertial Delay Model

      • Transport Delay Model



    • Simulation Deltas

    • Drivers

      • Driver Creation

      • Bad Multiple Driver Model



    • Generics

    • Block Statements

      • Guarded Blocks





  • Chapter 3 Sequential Processing

    • Process Statement

      • Sensitivity List

      • Process Example



    • Signal Assignment Versus Variable Assignment

      • Incorrect Mux Example

      • Correct Mux Example



    • Sequential Statements

    • IF Statements

    • CASE Statements

    • LOOP Statements

      • NEXT Statement



    • EXIT Statement

    • ASSERT Statement

      • Assertion BNF



    • WAIT Statements

      • WAIT ON Signal

      • WAIT UNTIL Expression

      • WAIT FOR time_expression

      • Multiple WAIT Conditions

      • WAIT Time-Out

      • Sensitivity List Versus WAIT Statement



    • Concurrent Assignment Problem

    • Passive Processes



  • Chapter 4 Data Types

    • Object Types

      • Signal

      • Variables

      • Constants



    • Data Types

      • Scalar Types

      • Composite Types

      • Incomplete Types

      • File Types



    • File Type Caveats

    • Subtypes



  • Chapter 5 Subprograms and Packages

    • Subprograms

      • Function

      • Conversion Functions

      • Resolution Functions

      • Procedures



    • Packages

      • Package Declaration

      • Deferred Constants

      • Subprogram Declaration

      • Package Body





  • Chapter 6 Predefined Attributes

    • Value Kind Attributes

      • Value Type Attributes

      • Value Array Attributes

      • Value Block Attributes



    • Function Kind Attributes

      • Function Type Attributes

      • Function Array Attributes

      • Function Signal Attributes

      • Attributes ’EVENT and ’LAST_VALUE

      • Attribute ’LAST_EVENT

      • Attribute ’ACTIVE and ’LAST_ACTIVE



    • Signal Kind Attributes

      • Attribute ’DELAYED

      • Attribute ’STABLE

      • Attribute ’QUIET

      • Attribute ’TRANSACTION



    • Type Kind Attributes

    • Range Kind Attributes



  • Chapter 7 Configurations

    • Default Configurations

    • Component Configurations

      • Lower-Level Configurations

      • Entity-Architecture Pair Configuration

      • Port Maps



    • Mapping Library Entities

    • Generics in Configurations

    • Generic Value Specification in Architecture

    • Generic Specifications in Configurations

    • Board-Socket-Chip Analogy

    • Block Configurations

    • Architecture Configurations



  • Chapter 8 Advanced Topics

    • Overloading

      • Subprogram Overloading

      • Overloading Operators



    • Aliases

    • Qualified Expressions

    • User-Defined Attributes

    • Generate Statements

      • Irregular Generate Statement



    • TextIO



  • Chapter 9 Synthesis

    • Register Transfer Level Description

    • Constraints

      • Timing Constraints

      • Clock Constraints



    • Attributes

      • Load

      • Drive

      • Arrival Time



    • Technology Libraries

    • Synthesis

      • Translation

      • Boolean Optimization

      • Flattening

      • Factoring

      • Mapping to Gates





  • Chapter 10 VHDL Synthesis

    • Simple Gate — Concurrent Assignment

    • IF Control Flow Statements

    • Case Control Flow Statements

    • Simple Sequential Statements

    • Asynchronous Reset

    • Asynchronous Preset and Clear

    • More Complex Sequential Statements

      • Four-Bit Shifter



    • State Machine Example



  • Chapter 11 High Level Design Flow

    • RTL Simulation

    • VHDL Synthesis

    • Functional Gate-Level Verification

    • Place and Route

    • Post Layout Timing Simulation

    • Static Timing



  • Chapter 12 Top-Level System Design

    • CPU Design

    • Top-Level System Operation

    • Instructions

    • Sample Instruction Representation

    • CPU Top-Level Design

      • Block Copy Operation





  • Chapter 13 CPU: Synthesis Description

    • ALU

    • Comp

    • Control

    • Reg

    • Regarray

    • Shift

    • Trireg



  • Chapter 14 CPU: RTL Simulation

    • Testbenches

      • Kinds of Testbenches

      • Stimulus Only

      • Full Testbench

      • Simulator Specific

      • Hybrid Testbenches

      • Fast Testbench



    • CPU Simulation



  • Chapter 15 CPU Design: Synthesis Results

  • Chapter 16 Place and Route

    • Place and Route Process

    • Placing and Routing the Device

      • Setting up a project





  • Chapter 17 CPU: VITAL Simulation

    • VITAL Library

    • VITAL Simulation Process Overview

    • VITAL Implementation

    • Simple VITAL Model

    • VITAL Architecture

      • Wire Delay Section

      • Flip-Flop Example



    • SDF File

      • VITAL Simulation



    • Back-Annotated Simulation



  • Chapter 18 At Speed Debugging Techniques

    • Instrumentor

    • Debugger

    • Debug CPU Design

      • Create Project

      • Specify Top-Level Parameters

      • Specify Project Parameters



    • Instrument Signals

    • Write Instrumented Design

    • Implement New Design

    • Start Debug

    • Enable Breakpoint

    • Trigger Position

    • Waveform Display

    • Set Watchpoint

    • Complex Triggers



  • Appendix A Standard Logic Package

  • Appendix B VHDL Reference Tables

  • Appendix C Reading VHDL BNF

  • Appendix D VHDL93 Updates

    • Alias

    • Attribute Changes

    • Bit String Literal

    • DELAY_LENGTH Subtype

    • Direct Instantiation

    • Extended Identifiers

    • File Operations

    • Foreign Interface

    • Generate Statement Changes

    • Globally Static Assignment

    • Groups

    • Incremental Binding

    • Postponed Process

    • Pure and Impure Functions

    • Pulse Reject

    • Report Statement

    • Shared Variables

    • Shift Operators

      • SLL — shift left logical

      • SRL — shift right logical

      • SLA — shift left arithmetic

      • SRA — shift right arithmetic

      • ROL — rotate left

      • ROR — rotate right



    • Syntax Consistency

    • Unaffected

    • XNOR Operator



  • Index

  • About the Author

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