Data Types 107
USE WORK.mux_types.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux8 IS
PORT(I0, I1, I2, I3, I4, I5,
PORT(I6, I7: IN std_logic;
PORT(sel : IN eightval; --line 2
PORT(q : OUT std_logic);
END mux8;ARCHITECTURE mux8 OF mux8 IS
BEGIN
WITH sel SELECT --line 3
Q <= I0 AFTER 10 ns WHEN 0, --line 4
Q <= I1 AFTER 10 ns WHEN 1, --line 5
Q <= I2 AFTER 10 ns WHEN 2, --line 6
Q <= I3 AFTER 10 ns WHEN 3, --line 7
Q <= I4 AFTER 10 ns WHEN 4, --line 8
Q <= I5 AFTER 10 ns WHEN 5, --line 9
Q <= I6 AFTER 10 ns WHEN 6, --line 10
Q <= I7 AFTER 10 ns WHEN 7; --line 11
END mux8;The package mux_typesdeclares a subtype eightval, which adds a con-
straint to base type INTEGER. The constraint allows an object of eightval
to take on values from 0 to 7.
The package is included in entity mux8, which has one of its input
ports seldeclared using type eightval. In the architecture at line 3, a
selected signal assignment statement uses the value of selto determine
which output is transferred to the output Q. If selwas not of the sub-
type eightval, but was strictly an integer type, then the selected signal
assignment would need a value to assign for each value of the type, or
an OTHERSclause. By adding the constraint to the integer type, all values
of the type can be directly specified.SUMMARY
In this chapter, we have examined the different types available in VHDL
to the designer. We discussed the following:How types can be used by three different types of objects: the
signal, variable, and constant.How signals are the main mechanism for the connection of
entities, and how signals are used to pass information
between entities.