VHDL Programming

Subprograms and Packages 113

created by port clkof entity dff. If there is a rising edge on the signal clk,

then the dvalue is transferred to the output q.

The most common use for a function is to return a value in an expres-

sion; however, there are two more classes of use available in VHDL. The

first is a conversion function, and the second is a resolution function. Con-

version functions are used to convert from one type to another. Resolution

functions are used to resolve bus contention on a multiply-driven signal.

Conversion Functions

Conversion functions are used to convert an object of one type to another.

They are used in component instantiation statements to allow mapping

of signals and ports of different types. This type of situation usually arises

when a designer wants to make use of an entity from another design that

uses a different data type.

Assume that designer A was using a data type that had the following

four values:

TYPE fourval IS (X, L, H, Z);

Designer B was using a data type that also contained four values, but

the value identifiers were different, as shown here:

TYPE fourvalue IS (‘X’, ‘ 0 ’, ‘ 1 ’, ‘Z’);

Both of these types can be used to represent the states of a four-state

value system for a VHDL model. If designer A wanted to use a model from

designer B, but designer B used the values from type fourvalueas the

interface ports to the model, then designer A cannot use the model with-

out converting the types of the ports to the value system used by designer

B. This problem can be solved through the use of conversion functions.

First, let’s write the function that converts between these two value

systems. The values from the first type represent these distinct states:

X—Unknown value

L—Logical 0 value

H—Logical 1 value

Z—High-impedance or open-collector value

The values from the second type represent these states:

‘X’—Unknown value