VHDL Programming

(C. Jardin) #1

Subprograms and Packages 115


RETURN ‘Z’;

END CASE;

END convert4val;

FUNCTION convert4value(S : fourvalue)
RETURN fourval IS
BEGIN
CASE S IS
WHEN ‘X’ =>
RETURN X;
WHEN ‘ 0 ’ =>
RETURN L;
WHEN ‘ 1 ’ =>
RETURN H;
WHEN ‘Z’ =>
RETURN Z;
END CASE;
END convert4value;
END reg;

ARCHITECTURE structure OF reg IS
COMPONENT dff
PORT(d, clk, clr : IN fourvalue;
q : OUT fourvalue);
END COMPONENT;
BEGIN
U1 : dff PORT MAP(convert4val(a(0)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(0));

U2 : dff PORT MAP(convert4val(a(1)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(1));

U3 : dff PORT MAP(convert4val(a(2)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(2));

U4 : dff PORT MAP(convert4val(a(3)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(3));

END structure;

This example is a 4-bit register built out of flip-flops. The type used in
the entity declaration for the register is a vector of type fourval. However,
the flip-flops being instantiated have ports that are of type fourvalue.A
type mismatch error is generated if the ports of entity register are mapped
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