118 Chapter Five
RETURN Z;
WHEN ZX =>
RETURN Z;
WHEN R0 =>
RETURN L;
WHEN R1 =>
RETURN H;
WHEN RX =>
RETURN X;
WHEN F0 =>
RETURN L;
WHEN F1 =>
RETURN H;
WHEN FX =>
RETURN X;
END CASE;
END convert9val;
END my_pack;USE WORK.my_pack.ALL;
ENTITY trans2 IS
PORT( a, b : INOUT nvector2;
PORT( enable : IN nineval);
END trans2;ARCHITECTURE struct OF trans2 IS
COMPONENT trans
PORT( x1, x2 : INOUT fourstate;
PORT( en : IN fourstate);
END COMPONENT;
BEGIN
U1 : trans PORT MAP(
convert4state(x1) => convert9val(a(0)),
convert4state(x2) => convert9val(b(0)),
en => convert9val(enable) );U2 : trans PORT MAP(
convert4state(x1) => convert9val(a(1)),
convert4state(x2) => convert9val(b(1)),
en => convert9val(enable) );
END struct;Each component is a bidirectional transfer device called trans. The
transdevice contains three ports. Ports x1and x2are inout ports, and
port enis an input port. When port enis an Hvalue,x1is transferred to
x2; and when port enis an Lvalue,x2is transferred to x1.
The transcomponents use type fourstatefor the port types; the
containing entity uses type nineval. Conversion functions are required
to allow the instantiation of the transcomponents in architecture struct
of entity trans2.