xvi Preface
range of types available for use in VHDL. Examples are given for each of
the types showing how they would be used in a real example. In Chapter
5 the concepts of subprograms and packages are introduced. The different
uses for functions are given, as well as the features available in VHDL
packages.
Chapter 6 introduces the five kinds of VHDL attributes. Each attribute
kind has examples describing how to use the specific attribute to the
designer’s best advantage. Examples are given which describe the pur-
pose of each of the attributes.
Chapters 7 and 8 will introduce some of the more advanced VHDL
features to the reader. Chapter 7 discusses how VHDL configurations
can be used to construct and manage complex VHDL designs. Each of
the different configuration styles are discussed along with examples
showing usage. Chapter 8 introduces more of the VHDL advanced top-
ics with discussions of overloading, user defined attributes, generate
statements, and TextIO.
The second section of the book consists of Chapters 9 through 11. Chap-
ters 9 and 10 discuss the synthesis process and how to write synthesiz-
able designs. These two chapters describe the basics of the synthesis
process including how to write synthesizeable VHDL, what is a technol-
ogy library, what does the synthesis process look like, what are con-
straints and attributes, and what does the the optimization process look
like. Chapter 11 discusses the complete high level design flow from VHDL
capture through VITAL simulation.
The third section of the book walks through a description of a small
CPU design from the VHDL capture through simulation, synthesis, place
and route, and VITAL simulation. Chapter 12 describes the top level of
the CPU design from a functional point of view. In Chapter 13 the RTL
description of the CPU is presented and discussed from a synthesis point
of view. Chapter 14 begins with a discussion of VHDL testbenches and
how they are used to verify functionality. Chapter 14 finishes the discus-
sion by describing the simulation of the CPU design. In Chapter 15 the
verified design is synthesized to a target technology. Chapter 16 takes
the synthesized design and places and routes the design to a target
device. Chapter 17 begins with a discussion of VITAL and ends with the
VITAL simulation of the placed and routed CPU design. Chapter 18 is a
new chapter that discusses the new technique of At-Speed debugging.
This chapter provides the reader with an in-depth look at how a hardware
implementation of the CPU design can help speed verification.
Finally there are three appendices at the end of the book to provide ref-
erence information. Appendix A is a listing of the IEEE 1164 STD_LOGIC