Configurations 183
END FOR;
END FOR;
END decode_map_con;The port map clause maps the port names of the component declara-
tions, called the formal ports, to the port names of the entities from the
library. The term used for the ports of the entities from the library being
mapped are actuals. The ports are mapped using named association. The
rules for mapping ports using named association in the configuration port
map clause are the same rules as used in the component instantiation
port map clause.
In the preceding example, component declaration inv, port a, is mapped
to entity inv, port x, of the actual entity. Component declaration inv, port
b, is mapped to entity inv, port y, of the actual entity. Using the configu-
ration port map clause can allow entities with completely different port
names to be mapped into existing architectures.Mapping Library Entities
Not only can the ports be mapped with the configuration statement, but
entities from libraries can be mapped to components as well. This capa-
bility allows the names of components to differ from the actual entities
being mapped to them. The designer can easily switch the entity used for
each component in the architecture from one entity to another. This feature
allows the designer to map component instances to different entities.
Let’s assume that one AND gate of the decoder needs to be imple-
mented differently from the others due to physical constraints of the device.
For instance instead of using a 3-input AND gate, a 3-input AND gate is
built using 2-input AND gates. Let’s start with the 2-input AND gate model
as shown below:LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
ENTITY and2 IS
PORT( a, b : in std_logic;
c : out std logic );
END and2;ARCHITECTURE behave OF and2 IS
BEGIN
c <= a and b;