192 Chapter Seven
END inv_gen1;
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LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
ENTITY and3 IS
GENERIC(int_rise, int_fall, ext_rise, ext_fall : time);
PORT( a1, a2, a3: IN std_logic;
PORT( o1: OUT std_logic);
END and3;ARCHITECTURE and3_gen1 OF and3 IS
BEGIN
and3_proc : PROCESS(a1, a2, a3)
VARIABLE state : std_logic;
BEGIN
state := a1 AND a2 AND a3;IF state = ‘ 1 ’ THEN
o1 <= state AFTER (int_rise + ext_rise);
ELSIF state = ‘ 0 ’ THEN
o1 <= state AFTER (int_fall + ext_fall);
ELSE
o1 <= state AFTER (int_fall + ext_fall);
END IF;END PROCESS and3_proc;
END and3_gen1;There are no local configurations specified at this level in the design
because this has nearly the same effect of mapping the generic values in
the architecture. Instead, a full configuration for entity decodeis specified
that maps the generics at all levels of the decoder. The entity and
architecture for the decoder, as shown in the following, are very similar
to the original example used earlier:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY decode IS
PORT( a, b, en : IN std_logic;
PORT( q0, q1, q2, q3 : OUT std_logic);
END decode;ARCHITECTURE structural OF decode IS
COMPONENT inv
PORT( a : IN std_logic;
PORT( b : OUT std_logic);
END COMPONENT;COMPONENT and3
PORT( a1, a2, a3 : IN std_logic;
PORT( o1 : OUT std_logic);
END COMPONENT;