Configurations 197
ENTITY board IS
GENERIC (qdelay, qbdelay : time);
PORT( clk, reset, data_in : IN std_logic;
PORT( data_out : OUT std_logic);
END board;ARCHITECTURE structural OF board IS
COMPONENT dff
GENERIC( g1, g2 : time);
PORT( p1, p2, p3, p4 : IN std_logic;
p5, p6 : OUT std_logic);
END COMPONENT;SIGNAL ground : std_logic := ‘ 1 ’;
SIGNAL int1, nc : std_logic;
BEGIN
U1 : dff
GENERIC MAP( g1 => qdelay,
GENERIC MAP( g2 => qbdelay)
PORT MAP( p1 => clk,
PORT MAP( p2 => data_in,
PORT MAP( p3 => reset,
PORT MAP( p4 => ground,
PORT MAP( p5 => int1,
PORT MAP( p6 => nc);U2 : dff
GENERIC MAP( g1 => qdelay,
GENERIC MAP( g2 => qbdelay)
PORT MAP( p1 => clk,
PORT MAP( p2 => int1,
PORT MAP( p3 => reset,
PORT MAP( p4 => ground,
PORT MAP( p5 => data_out,
PORT MAP( p6 => nc);
END structural;The entity and architecture shown are a simple 2-bit shift register
made from two D flip-flop (DFF) component instantiations. This example,
though relatively simple, shows how ports and generics are mapped at
different levels.
The component instance for component DFFin the architecture state-
ment part acts like a socket in the architecture for the board. When a
component instance is placed in the architecture, signals are used to con-
nect the component to the board, which is the architecture. The actual
chip is not connected to the socket until a configuration is specified for the
board entity. If all of the names of the socket ports and generics match
the names of the actual entity being used, then no mapping is needed. The
default mapping connects the chip to the socket. If the names are differ-
ent, or the number of ports are not the same, for the component instanti-