VHDL Programming

218 Chapter Eight

make the source being assigned to the signal. Now, whenever the target

signal type is changed, the source changes to match.

User-Defined Attributes

VHDL user-defined attributes are a mechanism for attaching data to VHDL

objects. The data attached can be used during simulation or by

another tool that reads the VHDL description. Data such as the disk file

name of the model, loading information, driving capability, resistance,

capacitance, physical location, and so on can be attached to objects. The

type and value of the data is completely user-definable. The value, when

specified, is constant throughout the simulation.

User-defined attributes can behave similar to entity generic values,

with one exception. Generics are only legal on entities, but user-defined

attributes can be assigned to the following list of objects:

Entity

Architecture

Configuration

Procedure

Function

Package

Type and Subtype

Constant

Signal

Variable

Component

Label

To see how user-defined attributes operate, let’s examine the following

description:

PACKAGE p_attr IS

TYPE t_package_type IS ( leadless,

TYPE t_package_type IS ( pin_grid,

TYPE t_package_type IS ( dip);

ATTRIBUTE package_type : t_package_type;