VHDL Programming

222 Chapter Eight

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

CLK

DFFX(0) DFFX(1) DFFX(2) DFFX(N)

Z(1) Z(2) Z(N)

A B

CLK

Figure 8-2
Irregular Generate
Statement Represen-
tation.

b <= z(4);

END long_way_shift;

The difference between the two architectures is that architecture

gen_shiftcould be specified with generic parameters such that different-sized

shift registers could be generated based on the value of the generic para-

meters. Architecture long_way_shiftis fixed in size and cannot be changed.

Irregular Generate Statement

The last example showed how a regular structure could be generated, but

in practice most structures are not completely regular. Most regular

structures have irregularities at the edges. This is shown by Figure 8-2.

In the last example, the irregularities were handled by the two

concurrent signal assignment statements. Following is another way to

handle the irregularities:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY shift IS

GENERIC ( len : INTEGER);

PORT( a, clk : IN std_logic;

PORT( b : OUT std_logic);

END shift;

ARCHITECTURE if_shift OF shift IS

COMPONENT dff

PORT( d, clk : IN std_logic;

PORT( q : OUT std_logic);

END COMPONENT;

SIGNAL z : std_logic_vector( 1 TO (len -1) );

BEGIN

g1 : FOR i IN 0 TO (len -1) GENERATE