VHDL Programming

234 Chapter Nine

DQ

CLK QB

EN

CLK

DIN

DOUT

Assignment Statement to

Dout

DQ

CLK QB

r1 r2
Figure 9-3
Register Transfer
Level with Compo-
nent Instances.

connected to the dinput of the next flip-flop. The selected signal assign-

ment to signal doutforms a muxoperation that selects between the two

flip-flop outputs.

This example could be rewritten as follows using register inference:

ENTITY datadelay IS

PORT( clk, din, en : IN BIT;

PORT( dout : OUT BIT);

END datadelay;

ARCHITECTURE inference OF datadelay IS

SIGNAL q1, q2 : BIT;

BEGIN

reg_proc: PROCESS

BEGIN

WAIT UNTIL clk’EVENT and clk = ‘ 1 ’;

q1 <= din;

q2 <= q1;

END PROCESS;

dout <= q1 WHEN en = ‘ 1 ’ ELSE

q2;