VHDL Programming

244 Chapter Nine

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Optimize

Map to Gates

VHDL RTL

Description

Unoptimized Boolean

Description

Optimized Boolean

Description

Gate Level

Netlist

Figure 9-8
Synthesis Process.

Boolean Optimization

The optimization process takes an unoptimized boolean description and

converts it to an optimized boolean description. In many designers’ eyes,

this is where the real work of synthesis gets done. The optimization

process uses a number of algorithms and rules to convert the unoptimized

boolean description to an optimized one. One technique is to convert the

unoptimized boolean description to a very low-level description (a pla

format), optimize that description (using pla optimization techniques),