Chapter 10 VHDL Synthesis

In this chapter, we focus on how to write VHDL that can

be read by synthesis tools. We start out with some simple

combinational logic examples, move on to some sequential

models, and end the chapter with a state machine de-

scription.

All of the examples are synthesized with the Exemplar

Logic Leonardo synthesis environment. The technology li-

brary used is an example library from Exemplar Logic. All

of the output data should be treated as purely sample out-

puts and not representative of how well the Exemplar

Logic tools work with real design data and real con-

straints.

10