VHDL Programming

Figure 10-9
A Sample Synthesized
Output.

shift_val(0) <= ‘ 0 ’;

END IF;

END PROCESS;

current: PROCESS

BEGIN

WAIT UNTIL clk’EVENT AND clk = ‘ 1 ’;

dout <= shift_val;

END PROCESS;

END synth;

The 4-bit type used for the input and output of the shifter is declared

in package shift_types. This package is used by entity shifterto de-

clare ports dinand dout. Ports clk,load, and left_rightare std_logic

signals used to control the functions of the shifter.

VHDL Synthesis 265