VHDL Programming

Top-Level System Design 293

This instruction loads the hex value 15 into register 1. The instruction

words look like those shown in Figure 12-3.

When the control unit decodes the opcode of the first word, it deter-

mines that the instruction is two words long and loads the second word

to complete the instruction.

The instructions implemented in the processor and their opcodes are

listed in Figure 12-4.

Not all of the possible instructions have been implemented in this

processor example to limit the complexity for ease of publication. Typical

commercial processors are much more complicated and have pipelined

instruction streams for faster execution. To reduce complexity, this example

is not pipelined.

CPU Top-Level Design

The next few sections contain the VHDL description for each of the CPU

components. First of all, a top-level package cpu_lib.vhdis needed to de-

scribe the signal types that are used to communicate between the CPU

components. Following is this package:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

package cpu_lib is

type t_shift is (shftpass, shl, shr, rotl, rotr);

subtype t_alu is unsigned(3 downto 0);

constant alupass : unsigned(3 downto 0) := “ 0000 ”;

Opcode DST

0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1

0 0 1 5

LoadI 1

Figure 12-3
Instruction Data.