VHDL Programming

296 Chapter Twelve

This model instantiates components cpuand memand specifies the nec-

essary signals to connect the components, as shown in Figure 12-5.

Component memis a memory device and contains the instructions and

data for the CPU to execute. Component cpuis an RTL implementation

of the CPU device that is simulated for correctness and synthesized to

implement the design.

Let’s now take a look at the description for the memory component to

see how it works. The memory is described in file mem.vhdshown in the

following:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

Cpu Mem

VMA

Ready

R/W

Addr

Data

Top

Clock Reset

Figure 12-5
Top Level of CPU
Design.