CPU: Synthesis Description 305
component reg
port( a : in bit16;
port( clk : in std_logic;
port( q : out bit16);
end component;component trireg
port( a : in bit16;
port( en : in std_logic;
port( clk : in std_logic;
port( q : out bit16);
end component;component control
port( clock : in std_logic;
port( reset : in std_logic;
port( instrReg : in bit16;
port( compout : in std_logic;
port( ready : in std_logic;
port( progCntrWr : out std_logic;
port( progCntrRd : out std_logic;
port( addrRegWr : out std_logic;
port( outRegWr : out std_logic;
port( outRegRd : out std_logic;
port( shiftSel : out t_shift;
port( aluSel : out t_alu;
port( compSel : out t_comp;
port( opRegRd : out std_logic;
port( opRegWr : out std_logic;
port( instrWr : out std_logic;
port( regSel : out t_reg;
port( regRd : out std_logic;
port( regWr : out std_logic;
port( rw : out std_logic;
port( vma : out std_logic
port( );
end component;component alu
port( a, b : in bit16;
port( sel : in t_alu;
port( c : out bit16);
end component;component shift
port ( a : in bit16;
port( sel : in t_shift;
port( y : out bit16);
end component;component comp
port( a, b : in bit16;