VHDL Programming

CPU: Synthesis Description 321

The resetof the description for the state machine contains the state

transitions for the rest of the instructions that have been implemented.

As mentioned previously, not all of the instructions have been imple-

mented and are left as an exercise for the reader.

Reg

The regentity is used for the address register and the instruction register.

These registers need to be able to capture the input data on a rising edge

of the clkinput and drive output qwith the captured data. The value of

input ais assigned to output qwhen a rising edge occurs on input clk.

The assignment is delayed by 1 nanosecond to remove delta delay problems

during simulation. A symbol for the regentity is shown in Figure 13-7.

The regsymbol contains three ports. Port ais the data input port, port

qis the data output port, and port clkcontrols when the data is stored

in the regentity. Following is the VHDL description for entity reg:

library IEEE;

use IEEE.std_logic_1164.all;

use work.cpu_lib.all;

entity reg is

port( a : in bit16;

port( clk : in std_logic;

port( q : out bit16);

end reg;

architecture rtl of reg is

begin

regproc: process

begin

wait until clk’event and clk = ‘ 1 ’;

q <= a after 1 ns;

end process;

end rtl;

q

clk

a

Reg

Figure 13-7
Reg Symbol.