CPU: Synthesis Description 323
architecture rtl of regarray is
type t_ram is array (0 to 7) of bit16;
signal temp_data : bit16;
begin
process(clk,sel)
variable ramdata : t_ram;
begin
if clk’event and clk = ‘ 1 ’ then
ramdata(conv_integer(sel)) := data;
end if;
temp_data <= ramdata(conv_integer(sel)) after 1 ns;
end process;process(en, temp_data)
begin
if en = ‘ 1 ’ then
q <= temp_data after 1 ns;
else
q <= “ZZZZZZZZZZZZZZZZ” after 1 ns;
end if;
end process;end rtl;The first process models the part of the RAM that stores the data. This
process contains a local variable ramdatathat is used to store the data
written to the regarrayentity. When the clksignal has a rising edge, the
location selected by input selis updated with the new value. This process
also writes the location to a signal called temp_datato pass the value to
the second process. The reason for this is that this model was written
using VHDL 87, and variables cannot be shared between processes. In
VHDL 93, sharing variables between processes is legal but has other syn-
thesis ramifications.
The second process is used to read data from the regarray. Whenever
input selchanges, the first process updates the value of temp_data. Sig-
nal temp_datais passed to the second process to pass the memory data.
The second process outputs the value of temp_dataif the ensignal is ‘ 1 ’;
otherwise, it puts out Zvalues. The Zvalues signify that the regarray
entity is not driving the output when the eninput is unasserted.
A smart synthesis tool reading this design can realize that the regarray
entity can be implemented by a RAM device in the target technology and
provide the proper mapping. For instance, if the design were to be mapped
to an FPGA technology that included RAM in the architecture, the syn-
thesis tool could map the regarrayentity to an onboard RAM device. Us-
ing such an implementation instead of a set of flip-flops and gates creates
a smaller and faster implementation.