VHDL Programming

330 Chapter Fourteen

Top Level

Stimulus

Driver

Design

Under

Test

Figure 14-1
Top-Level Design
Structure.

Testbenches

A testbench is used to verify the functionality of a design. The testbench

allows the design to verify the functionality of the design at each step

in the HDL synthesis-based methodology. When the designer makes a

small change to fix an error, the change can be tested to make sure that

it did not affect other parts of the design. New versions of the design can

be verified against known good results to verify compatibility.

A testbench is at the highest level in the hierarchy of the design. The

testbench instantiates the design under test (DUT). The testbench provides

the necessary input stimulus to the DUT and examines the output from

the DUT. Figure 14-2 shows a block diagram of how this process appears.

The testbench encapsulates the stimulus driver, known good results,

and DUT, and contains internal signals to make the proper connections.

The stimulus driver drives inputs into the DUT. The DUT responds to the

input signals and produces output results. Finally, a compare function

within the testbench compares the results from the DUT against those

known good results and reports any discrepancies. That is the basic

function of a testbench, but there are a number of methods of writing a

testbench and each method has advantages and disadvantages.