CPU: RTL Simulation 335
-- read din value
read(l, tmpdin, good_val);
assert good_val REPORT “bad din value “;clk <= tmpclk;
ld <= tmpld;
up_dwn <= tmpup_dwn;
clk_en <= tmpclk_en;
din <= tmpdin;END LOOP;
ASSERT false REPORT “Test complete”;
WAIT;
END PROCESS;
END;The beginning of the testbench declares entity testbenchas an entity
with no ports. This is completely legal as the testbench is the topmost en-
tity and does not interract with any other entities.
Next is the architecture declaration. The architecture uses a number
of packages including IEEE standard packages and counter. The next
section in the model declares the component for the DUT (Device Under
Test), the counter. The ports and types on this component should match
the DUT. Next, the local interconnect signals are declared. After the archi-
tecture declaration section, the DUT component is instantiated and con-
nected to the local interconnect signals.
A process called testis declared which contains the stimulus generation
capability. First, a number of local variables are declared to receive data
from the TextIO procedures used to read the stimulus information from
a file. TextIO can only assign to variable objects not signals; therefore, local
variables are assigned by the TextIO procedures, and these variables are
assigned to the internal interconnect signals.
Inside the process is a single whileloop that reads data from the
stimulus file until an end-of-file condition is reached. Each pass through
the loop reads another line from the file and reads the appropriate data
from that line.
The first data read from the line is the time that this vector is to be
applied. The process checks to make sure that the value read is a valid
number. If not, the line is discarded because it does not represent a
valid stimulus line.This allows comment lines to be inserted in the vector
files. If a valid number was not read, the process skips this iteration
through the loop and goes to the next iteration using the nextclause.
If the value read was a good number, then the vector is assumed to be
valid. The process reads each data value from the vector and applies the
values to the locally declared variables.