VHDL Programming

Behavioral Modeling 17

A

B

C

Figure 2-1
AND Gate Symbol.

END and2_behav;

The AND gate has two inputs a, band one output c, as shown in Figure

2-1. The value of signal cmay be assigned a new value whenever either

aor bchanges value. With an AND gate, if ais a ‘ 0 ’and bchanges from a

‘ 1 ’to a ‘ 0 ’, output cdoes not change. If the output does change value, then

a transaction occurs which causes an event to be scheduled on signal c;

otherwise, a transaction occurs on signal c.

The entity design unit describes the ports of the and2gate. There are

two inputs aand b, as well as one output c. The architecture and2_behav

for entity and2contains one concurrent signal assignment statement. This

statement is sensitive to both signal aand signal bby the fact that the

expression to calculate the value of cincludes both aand bsignal values.

The value of the expression aand bis calculated first, and the resulting

value from the calculation is scheduled on output c, 5 nanoseconds from

the time the calculation is completed.

The next example shows more complicated signal assignment state-

ments and demonstrates the concept of concurrency in greater detail. In

Figure 2-2, the symbol for a four-input multiplexer is shown.

This is the behavioral model for the mux:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY mux4 IS

PORT ( i0, i1, i2, i3, a, b : IN std_logic;

PORT ( i0, i1, i2, i3, a, q : OUT std_logic);

END mux4;

ARCHITECTURE mux4 OF mux4 IS

SIGNAL sel: INTEGER;

BEGIN

WITH sel SELECT

q <= i0 AFTER 10 ns WHEN 0,

q <= i1 AFTER 10 ns WHEN 1,