Chapter 15 CPU Design: Synthesis Results

After the CPU has been functionally verified, the design

can be implemented in actual hardware. This chapter

describes the synthesis process and synthesis results of

the CPU RTL description. The VHDL design description

is optimized and mapped to a programmable logic device.

As opposed to an ASIC device, these devices can be pro-

grammed by designers at their desks, and most can be

reprogrammed to fix errors later.

A synthesis tool is used to read in the VHDL description

and map the description to the target programmable logic

device. The synthesis tool reads all the VHDL source files,

links them together (elaborate), optimizes the design, and

then maps the optimized description to the target tech-

nology. The synthesis tool used is the Leonardo Spectrum

synthesis tool from Exemplar Logic. This is a popular syn-

thesis tool in the FPGA (Field Programmable Gate Array)

market and produces very good results quickly.

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