VHDL Programming

(C. Jardin) #1

Behavioral Modeling 19


ABQ

00I0

10I1

01I2

11I3

Figure 2-3
Mux Functional
Table.


matches does the assign, and the other matching statements’values are
ignored.
The first statement is called a selected signal assignment and selects
among a number of options to assign the correct value to the target sig-
nal. The target signal in this example is the signal q.
The expression (the value of signal selin this example) is evaluated,
and the statement that matches the value of the expression assigns the
value to the target signal. All of the possible values of the expression must
have a matching choice in the selected signal assignment (or an OTHERS
clause must exist).
Each of the input signals can be assigned to output q, depending on the
values of the two select inputs, aand b. If the values of aor bare unknown
values, then the last value, ‘X’(unknown), is assigned to output q. In this
example, when one of the select inputs is at an unknown value, the out-
put is set to unknown.
Looking at the model for the multiplexer, it looks like the model will
not work as written. It seems that the value of signal selis used before
it is computed. This impression is received from the fact that the second
statement in the architecture is the statement that actually computes the
value for sel. The model does work as written, however, because of the
concept of concurrency.
The second statement is sensitive to signals aand b. Whenever either
aor bchanges value, the second statement is executed, and signal selis
updated. The first statement is sensitive to signal sel. Whenever signal
selchanges value, the first signal assignment is executed.
If this example is processed by a synthesis tool, the resulting gate
structure created resembles a 4 to 1 multiplexer. If the synthesis library
contains a 4 to 1 multiplexer primitive, that primitive may be generated
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