of driving all the flip flops in the design. This requires a clock buffer
rather than a standard buffer. In Figure 16-11 the clock port is assigned
to a dedicated clock buffer port.
Now that all the parameters have been specified, the place and route
process can be run by selecting the Processing Start Compilation menu
item. After the compilation process completes, the results are displayed
(see Figure 16-12).SUMMARY
In this chapter, the netlist output from the synthesis tool was read by the
place and route tool, and an implementation of the netlist was generated.
We examined the process required to run the place and route tool, the
inputs to the place and route tool, and the outputs from it. In the next
chapter, we examine how to verify that the design created from the place
and route tool meets our requirements.Place and Route 377
Figure 16-11
Specify Pin
Assignments.