VHDL Programming

Package contains procedures and functions for accurate delay modeling,

timing checks, and timing error reporting. The VITAL Primitives Package

contains built-in primitives that are optimized for simulator performance.

Most VITAL-compliant simulators build the primitives package into the

simulator for optimum performance.

VITAL contains two styles of modeling that can be back-annotated with

SDF timing data for timing-accurate simulation. The first style, VITAL

level 1, uses only VITAL primitives for modeling the behavior of the

design. The second, VITAL level 0, has the capability to back-annotate

timing, but uses behavioral statements to describe the functionality of the

design. VITAL level 1 descriptions can be accelerated by VITAL-compliant

simulators because the constructs used are built into the simulator. VITAL

level 0 descriptions may not be accelerated because these descriptions use

behavioral constructs which may not be built in.

Simple VITAL Model

To understand how the VITAL modeling process works, a simple VITAL

model is examined. The model describes the behavior of a 2-input AND

gate. The symbol for the AND gate is shown in Figure 17-3.

The AND gate has two inputs,in1and in2, and an output y. When

modeled with VITAL, this device has an input delay on inputs in1and

CPU:Vital Simulation 383

in1 Input Delay

Output Delay

int2 -> y

in1

y

in2

Figure 17-3
VITAL AND Gate.