VHDL Programming

end for;

end topconrtl;

configuration topconstruct of top is

for behave

for U1 : cpu use entity work.cpu(EPF10K10TC144_a3);

end for;

end for;

end topconstruct;

Configuration topconrtlspecifies the rtlimplementation configuration

for entity top, and configuration topconstructspecifies the structural

implementation. Notice that the structural architecture was named the

same as the device that was implemented by the place and route tools.

To complete the simulation setup process, the final compilations

needed are shown here:

vcom top.vhd

vcom topconstruct.vhd

After these steps, the design is ready for simulation. To load the design

into the simulator, the following command is executed:

vsim topconstruct

The simulator brings up its windows and begins the simulation. If the

simulation is run ahead 500 nanoseconds, we can see the CPU start the

reset sequence as instructions are fetched. This is shown in Figure 17-5.

396 Chapter Seventeen

Figure 17-5
The Simulator
Window.