VHDL Programming

(C. Jardin) #1
until the design stops working to determine the maximum speed that
the design will run. By running the design through the entire simulation,
the functionality and timing of the design can be verified for correctness.
When the design meets the functionality and timing requirements, the
design can be signed off and built.

SUMMARY


In this chapter, we examined VITAL simulation and how to perform
VITAL simulation on the CPU design. The rest of the book contains use-
ful appendices that describe some of the standard types, functions, and
procedures used throughout the book.

398 Chapter Seventeen

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