VHDL Programming

Instrumentor

The designer reads the VHDL design into the instrumentor and specifies

which signals to probe and which breakpoints to enable. The instrumentor

generates a new VHDL description of the design with the IICE core added

and connected to the appropriate places in the design. Once the new VHDL

description has been created, the designer synthesizes, and place and route

the new VHDL description. In an FPGA design environment, the device is

programmed with the new device file created by place and route.

Debugger

Once the board is powered up, and the FPGA device is programmed with

the new device file from place and route, the debugger can communicate

with the device through the JTAG port. The debugger also reads the data-

base file created by the Instrumentor and the original VHDL source files.

The instrumentor database relates the real signals on the device to the

location of the signals in the original HDL.

Debug CPU Design

Let’s now look at the process of debugging the CPU design using the

Bridges2Silicon Debugger. The first step is to create a project containing

all of the HDL files for the design.

At Speed Debugging Techniques 401

HDL

Sources

IICE

Implement

(Synthesis, P&R)

SOC

Implement

(Synthesis, P&R)

Bridges2Silicon

Instrumentor

Instrumented

HDL

Sources

B2S

Project

Bridges2Silicon

Instrumentor

B2S

Project

Bridges2Silicon

Debugger

JTAG

Bridges2Silicon

Debugger

JTAG

Figure 18-2
Bridges2Silicon
Debugger Overview.