will communicate with the JTAG port and the debugger on the host
platform. Use the dialog box shown in Figure 18-7 to set up the device
and IICE configuration settings.1.Device family. We use the Altera Apex technology.
2.JTAG port. The choices are b2sand builtin. We will choose builtin
so that we can use JTAG communication with the JTAG tap controller
already present in the Altera device. This choice is used predominately
and b2sis only used when the board containing the device is not connected
to the JTAG chain on the board.3.Type of RAM. This parameter specifies the type of RAM to be used for
the sample buffer that stores internal signal data. The choices are block-
ram, logic, and behavioral. This example will use blockram, the most com-
mon selection and the most efficient. This selection will build the sample
buffer from blockrams available on the FPGA device. If the logic choice is
selected, the sample buffer will be built from flip-flops in user logic. This
choice is used when there is limited blockram available and is not as effi-
cient as blockram. The third choice is behavioral and will generate a
behavioral model for the sample buffer. This choice will let the synthesis
tool choose the sample buffer implementation based on available resources.
4.Sample clock. This parameter specifies a signal that will be used to
clock the data into the sample buffer. This signal can be any signal in the
design but must be a clocklike signal. For instance, this signal should be
the output of a register so that it does not contain glitches. In this example
the signal /clkwill be used.5 .Sample depth. This parameter specifies how many samples are gath-
ered when a trigger occurs. Depending on how much data are required
to find a bug, this value can be any power of 2 that will fit into the Buffer
Type specified for the device. In this example, the value 256 will be used.Instrument Signals
Now that the design has been compiled and the communication parameters
specified, the signals to be instrumented can be selected. For this example
we are going to debug the control block. All breakpoints and signals in the
control block for the reset sequence will be instrumented for use later dur-
ing debugging. The debugger GUI shows only the signals and breakpoints
that can be instrumented. Clicking the Radiobutton next to a signal or
breakpoint will instrument that signal or breakpoint. Figure 18-8 shows the
Radio buttons for the reset sequence selected for sampling and debugging.404 Chapter Eighteen