Appendix B VHDL Reference Tables
This appendix focuses on tables of information that are useful when writ-
ing VHDL descriptions. Most of the information in the tables is available
in the text of the book, however, these tables consolidate the information
into one area for easy reference.
Table B-1 lists all of the different kinds of statements alphabetically
and includes an example usage.Table B-1
Statement or Clause Example(s)
Access Type TYPE access_type IS ACCESS type_to_be_accessed;Aggregate record_type := (first, second, third);Alias ALIAS opcode : BIT_VECTOR (0 TO 3) IS
INSTRUCTION(10 TO 13);Architecture ARCHITECTURE architecture_name OF entity
name IS
--declare some signals here
BEGIN
--put some concurrent statements here
END architecture_name;Array Type TYPE array_type IS ARRAY (0 TO 7) OF BIT;Assert ASSERT x > 10 REPORT “x is too small”
SEVERITY ERROR;Attribute Declaration ATTRIBUTE attribute_name : attribute_type;Attribute Specification ATTRIBUTE attribute_name OF
entity_name : entity_class IS value;Block Statement block_name : BLOCK
--declare some stuff here
BEGIN
--put some concurrent statements here
END BLOCK block_name;Case Statement CASE some_expression IS
WHEN some_value =>
--do_some_stuff
WHEN some_other_value =>
--do_some_other_stuff
WHEN OTHERS =>
--do_some_default_stuff
END CASE;