VHDL Programming

Appendix B: VHDL Reference Tables 439

Table B-1

Statement or Clause Example(s)

Process Statement PROCESS (signal1, signal2, signal3)

--declare some stuff

BEGIN

--do some stuff

END PROCESS;

Record Type TYPE record_type IS

RECORD

field1 : field1_type;

field2 : field2_type;

END RECORD;

Report Clause ASSERT x = 10 REPORT “some string”;

Return Statement RETURN;

RETURN (x + 10);

Selected Signal Assignment WITH z SELECT

x <= 1 AFTER 5 NS WHEN 0,

2 AFTER 5 NS WHEN 1,

3 AFTER 5 NS WHEN OTHERS;

Severity Clause ASSERT x > 5 REPORT “some string”SEVERITY

ERROR;

Signal Assignment a <= b AFTER 20 NS;

Signal Declaration SIGNAL x : xtype;

Subtype Declaration SUBTYPE bit8 IS INTEGER RANGE 0 TO 255;

Transport Signal Assignment x <= TRANSPORT y AFTER 50 NS;

Type Declaration TYPE color is (red, yellow, blue, green, orange);

TYPE small_int is 0 to 65535;

Use Clause USE WORK.my_package.all;

Variable Declaration VARIABLE variable_name : variable_type;Wait

Statement WAIT ON a, b, c;

WAIT UNTIL clock’EVENT AND clock = ‘ 1 ’;

WAIT FOR 100 NS;

WAIT ON a, b UNTIL b > 10 FOR 50 NS;

While Loop WHILE x > 15 LOOP

--do some stuff

END LOOP;

Table B-2 lists all of the predefined attributes that retrieve infor-

mation about VHDL type data. The descriptions are necessarily terse

to fit into the table cells; see Chapter 6,“Predefined Attributes”for

more detailed information.