452 Appendix D: VHDL93 Updates
`INSTANCE_NAME—returns a string that describes the path to the
entity starting at the root of the design. The `INSTANCE_NAME
attribute also includes the names of instantiated entities. These
entities are specified using a label@entity(architecture)syntax.Bit String Literal
Bit string literals are a handy way in VHDL87 to assign bit_vector
values. For instance instead of having to explicitly enumerate each bit value
when assigning to a bit_vectoran octal or hexadecimal notation can
be used as shown here:SUBTYPE bit16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);VARIABLE bus_value : bit16;-- these won’t work with VHDL87
bus_value := “ 0101010101010101 ”; --- or
bus_value := O” 052525 ”; -- or
bus_value := X” 5555 ”;In VHDL93 this concept is extended to types std_logic_vector.DELAY_LENGTH Subtype
In VHDL87 most time delays were specified with a type TIME. Type TIME
included negative and positive time values. Most uses of TIMErequired only
positive values of TIME. Therefore in VHDL93 a new type in package STANDARD
has been created, and called DELAY_LENGTH.It’s definition is shown here:SUBTYPE DELAY_LENGTH IS TIME RANGE 0 FS TO TIME`HIGH;
As can be seen this type only includes the positive values of TIME.
Compiler writers can optimize the compilation and simulation processes
more with this knowledge.Direct Instantiation
In VHDL87 an entity from a particular library could not be directly
instantiated in an architecture. A component was declared, instantiated,