u1: mux4 PORT MAP( k0 => s0, k1 => s1, k2 => s2, en =>
‘ 1 ’, q => outp);In the example above the value 1 is mapped to port en. In VHDL87 a
separate signal would have to be created, assigned to the value 1 , and
then mapped to port en.
The globally static value does not have to be just a simple value, it can
be any expression known at compile time that matches the type of the port.Groups
It is sometimes useful while modeling to declare an attribute that is to
apply to more than one object. Especially in writing synthesizable models
some attributes are useful to describe behavior for an entire section of a
model. In VHDL87 there was no way to describe this type of attribute
structure. VHDL93 has the concept of groups which allows an attribute to
pertain to all objects in the group.
A group starts with a group template declaration such as shown here:GROUP timing_arc IS (SIGNAL, SIGNAL);This describes a group template called timing_arcthat is a group of
two signal objects. After the group template is declared a group declaration
can be declared as shown here:GROUP clk_to_q : timing_arc(clk, q);
GROUP rst_to_q : timing_arc(rst, q);
GROUP set_to_q : timing_arc(set, q);These declarations show three separate group declarations named
clk_to_q,rst_to_q, and set_to_q. Each of these groups describe a group
object with two signals in the group. Once declared these groups can be
operated on as a single object. For instance, if the following attribute is
declared:ATTRIBUTE prop_delay IS DELAY_LENGTH;then the following attributes can be applied to the group.ATTRIBUTE prop_delay OF clk_to_q : GROUP IS 2.3 NS;
ATTRIBUTE prop_delay OF rst_to_q : GROUP IS 3.1 NS;
ATTRIBUTE prop_delay OF set_to_q : GROUP IS 2.7 NS;Appendix D: VHDL93 Updates 457