Behavioral Modeling 29
ARCHITECTURE better OF mux IS
BEGIN
q <= i0 WHEN a = ‘ 0 ’ AND b = ‘ 0 ’ ELSE
i1 WHEN a = ‘ 1 ’ AND b = ‘ 0 ’ ELSE
i2 WHEN a = ‘ 0 ’ AND b = ‘ 1 ’ ELSE
i3 WHEN a = ‘ 1 ’ AND b = ‘ 1 ’ ELSE
‘X’; --- unknown
END better;Generics
Generics are a general mechanism used to pass information to an instance
of an entity. The information passed to the entity can be of most types
allowed in VHDL. (Types are covered in detail later in Chapter 4, “Data
Types.”)
Why would a designer want to pass information to an entity? The
most obvious, and probably most used, information passed to an entity is
delay times for rising and falling delays of the device being modeled.
Generics can also be used to pass any user-defined data types, including
information such as load capacitance, resistance, and so on. For synthesis
parameters such as datapath widths, signal widths, and so on, can be
passed in as generics.
All of the data passed to an entity is instance-specific information. The
data values pertain to the instance being passed the data. In this way, the
designer can pass different values to different instances in the design.
The data passed to an instance is static data. After the model has been
elaborated (linked into the simulator), the data does not change during
simulation. Generics cannot be assigned information as part of a simula-
tion run. The information contained in generics passed into a component
instance or a block can be used to alter the simulation results, but results
cannot modify the generics.
The following is an example of an entity for an AND gate that has three
generics associated with it:ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT( a, b : IN BIT;
PORT( c : OUT BIT);
END AND2;This entity allows the designer to pass in a value for the rise and fall