40 Chapter Three
Process Statement
In an architecture for an entity, all statements are concurrent. So where
do sequential statements exist in VHDL? There is a statement called
the process statementthat contains only sequential statements. The
process statement is itself a concurrent statement. A process statement
can exist in an architecture and define regions in the architecture
where all statements are sequential.
A process statement has a declaration section and a statement part. In
the declaration section, types, variables, constants, subprograms, and so on
can be declared. The statement part contains only sequential statements.
Sequential statements consist of CASEstatements,IF THEN ELSEstate-
ments,LOOPstatements, and so on. We examine these statements later in
this chapter. First, let’s look at how a process statement is structured.Sensitivity List
The process statement can have an explicit sensitivity list. This list defines
the signals that cause the statements inside the process statement to
execute whenever one or more elements of the list change value. The sen-
sitivity list is a list of the signals that will cause the process to execute.
The process has to have an explicit sensitivity list or, as we discuss later,
a WAITstatement.
As of this writing, synthesis tools have a difficult time with sensitivity
lists that are not fully specified. Synthesis tools think of process state-
ments as either describing sequential logic or combinational logic. If a
process contains a partial sensitivity list, one that does not contain every
input signal used in the process, there is no way to map that functionality
to either sequential or combinational logic.Process Example
Let’s look at an example of a process statement in an architecture to see
how the process statement fits into the big picture, and discuss some more
details of how it works. Following is a model of a two-input NAND gate:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY nand2 IS