42 Chapter Three
c <= temp AFTER 6 ns;
ELSIF (temp = ‘ 0 ’) THEN
c <= temp AFTER 5 ns;
ELSE
c <= temp AFTER 6 ns;
END IF;The process contains an explicit sensitivity list with two signals con-
tained in it:PROCESS( a, b )The process is sensitive to signals aand b. In this example,aand bare
input ports to the model. Input ports create signals that can be used as
inputs; output ports create signals that can be used as outputs; and inout
ports create signals that can be used as both. Whenever port aor bhas a
change in value, the statements inside of the process are executed. Each
statement is executed in serial order starting with the statement at the
top of the process statement and working down to the bottom. After all of
the statements have been executed once, the process waits for another
change in a signal or port in its sensitivity list.
The process declarative part declares one variable called temp. Its type
is std_logic. This type is explained in Appendix A,“Standard Logic
Package,”as it is used throughout the book. For now, assume that the type
defines a signal that is a single bit and can assume the values 0, 1, and
X. Variable tempis used as temporary storage in this model to save the pre-
computed value of the expression (aand b). The value of this expression is
precomputed for efficiency.Signal Assignment Versus Variable Assignment
The first statement inside of the process statement is a variable assign-
ment that assigns a value to variable temp. In the previous chapter, we
discussed how signals received values that were scheduled either after
an amount of time or after a delta delay. A variable assignment happens
immediately when the statement is executed. For instance, in this
model, the first statement has to assign a value to variable tempfor the
second statement to use. Variable assignment has no delay; it happens
immediately.