VHDL Programming

(C. Jardin) #1

64 Chapter Three


WAIT Time-Out


There are instances while designing a model when you are not sure that a
condition will be met. To prevent the WAITstatement from waiting for-
ever, add a time-out clause. The time-out clause allows execution to
proceed whether or not the condition has been met. Be careful, though,
because this method can cause erroneous behavior unless properly handled.
The following example shows this problem:

ARCHITECTURE wait_example of wait_example IS
SIGNAL sendB, sendA : std_logic;
BEGIN
sendA <= ‘ 0 ’;
A : PROCESS
BEGIN
WAIT UNTIL sendB = ‘ 1 ’;
sendA <= ‘ 1 ’ AFTER 10 ns;

WAIT UNTIL sendB = ‘ 0 ’;
sendA <= ‘ 0 ’ AFTER 10 ns;

END PROCESS A;

B : PROCESS
BEGIN
WAIT UNTIL sendA = ‘ 0 ’;
sendB <= ‘ 0 ’ AFTER 10 ns;

WAIT UNTIL sendA = ‘ 1 ’;
sendB <= ‘ 1 ’ AFTER 10 ns;

END PROCESS B;
END wait_example;

This architecture has two processes that communicate through two
signals,sendAand sendB. This example does not do anything real but is
a simple illustration of how WAITstatements can wait forever, a condition
commonly referred to as deadlock.
During simulator initialization, all processes are executed exactly once.
This allows the processes to always start at a known execution point at the
start of simulation. In this example, the process labeled A executes at
startup and stops at the following line:

WAIT UNTIL sendB = 1;

The process labeled Balso executes at startup. Execution starts at the
first line of the process and continues until this line:
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